Defect-oriented testing for nano-metric CMOS VLSI circuit
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Main Author: | |
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Other Authors: | |
Format: | Unknown |
Published: |
Dordrecht
Springer
2007
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Edition: | 2nd ed. |
Series: | Frontiers in electronic testing
34 |
Subjects: | |
Online Access: | Click Here to View Status and Holdings. |
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100 | 1 | # | |a Sachdev, Manoj |
245 | 1 | 0 | |a Defect-oriented testing for nano-metric CMOS VLSI circuit |c by Manoj Sachdev and Jose Pineda de Gyvez |h electronic resource |
250 | # | # | |a 2nd ed. |
260 | # | # | |a Dordrecht |b Springer |c 2007 |
300 | # | # | |a xxi, 328 p. |b ill. |c 24 cm |
490 | 1 | # | |a Frontiers in electronic testing |v 34 |
500 | # | # | |a New edition of: Defect oriented testing for CMOS analog and digital circuits, 1998 |
538 | # | # | |a Mode of access: World Wide Web |
650 | # | 0 | |a Metal oxide semiconductors, Complementary |x Testing |
650 | # | 0 | |a Metal oxide semiconductors, Complementary |x Defects |x Defects |
650 | # | 0 | |a Integrated circuits |x Very large scale integration |x Testing |
650 | # | 0 | |a Integrated circuits |x Very large scale integration |x Defects |
700 | 1 | # | |a Sachdev, Manoj |t Defect oriented testing for CMOS analog and digital circuits |
700 | # | # | |a Pineda de Gyvez, Jose |
856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=379542 |
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