Logical effort designing fast CMOS circuits

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Bibliographic Details
Main Author:	Sutherland, Ivan
Other Authors:	Sproull, Bob, Harris, David
Format:	Unknown
Published:	San Francisco Morgan Kaufmann 1999
Subjects:	Metal oxide semiconductors, Complimentary > Design and construction Delay faults (Semiconductors) Logic design
Online Access:	Click Here to View Status and Holdings.
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MARC


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020	#	#	\|a 1558605576
090	0	0	\|a TK7871.99.M44 \|b S88 1999
100	1	#	\|a Sutherland, Ivan
245	1	1	\|a Logical effort \|b designing fast CMOS circuits \|c Ivan Sutherland, Bob Sproull, David Harris
260	#	#	\|a San Francisco \|b Morgan Kaufmann \|c 1999
300	#	#	\|a xv, 239 p. \|b ill. \|c 23 cm
504	#	#	\|a Includes bibliographical references and index
650	#	0	\|a Metal oxide semiconductors, Complimentary \|x Design and construction
650	#	0	\|a Delay faults (Semiconductors)
650	#	0	\|a Logic design
700	1	#	\|a Sproull, Bob
700	#	#	\|a Harris, David
856	4	0	\|z Click Here to View Status and Holdings. \|u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=192475
964	#	#	\|c BOK \|d 01
040	#	#	\|a Shah Alam
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