Formal VLSI correctness verification proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design

Formal VLSI correctness verification proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design

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Bibliographic Details
Corporate Authors: IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design, Interuniversity Micro-Electronics Center
Other Authors: Claesen, Luc J. M
Format: Unknown
Published: Amsterdam New York North-Holland 1990
Series:VLSI design methods 2
Subjects:
Computer-aided design > Congresses
Integrated circuits > Very large scale integration > Design and construction > Data processing > Congresses
Integrated circuits > Very large scale integration > Testing > Congresses > Congresses
Online Access:Click Here to View Status and Holdings.
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