RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design
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Main Author: | |
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Format: | Book |
Language: | English |
Published: |
Tualatin, OR
SUTHERLAND HDL,
2017
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Edition: | Print book : English |
Subjects: | |
Online Access: | Click Here to View Status and Holdings. |
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005 | 2022026165059 | ||
008 | 220530t2017 -US #g# ##001 #beng#D | ||
020 | # | # | |a 9781546776345 |q paperback |
040 | # | # | |a UiTM |b eng |c UiTM |e rda |
041 | 0 | # | |a eng |
090 | 0 | 0 | |a TK7885.7 |b .S88 2017 |
100 | 1 | # | |a Sutherland, Stuart |e author |
245 | 0 | 0 | |a RTL Modeling with SystemVerilog for Simulation and Synthesis |b using SystemVerilog for ASIC and FPGA design |c Stuart Sutherland |
246 | 3 | # | |a RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design |
250 | # | # | |a Print book : English |
264 | # | 1 | |a Tualatin, OR |b SUTHERLAND HDL, |c 2017 |
264 | # | 4 | |c ©2017 |
300 | # | # | |a xxxi, 453 pages |b illustrations |c 23 cm |
336 | # | # | |a text |2 rdacontent |
337 | # | # | |a unmediated |2 rdamedia |
338 | # | # | |a volume |2 rdacarrier |
504 | # | # | |a Includes bibliographical references and index |
526 | 0 | # | |a bachelor of Electronic (Hons) Engineering |b electronics and computer engineering |5 universiti teknologi mara |
546 | # | # | |a In English |
650 | 1 | 0 | |a Verilog (Computer hardware description language) |
650 | 2 | 0 | |a Electronic digital computers |x Design and construction |
650 | 2 | 0 | |a Computer simulation |
856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=976572 |
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