Digital Design & Computer Organisation
Sequential Circuit Design : Synchronous and asynchronous FSM design, Basic design steps, State encoding techniques, VHDL coding of state machines, Analysis of sequential circuits, Algorithmic State Machine (ASM) charts. HDL : Introduction to HDL, VHDL, Library, Entity, Architecture, Modeling styles,...
Saved in:
Main Authors: | , |
---|---|
Format: | Book |
Language: | English |
Published: |
Pune
Technical Pub. Pune
2003
|
Edition: | Third Revised Edition-2008 |
Subjects: | |
Online Access: | Click Here to View Status and Holdings. |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
MARC
LEADER | 00000nam a2200000#i 4501 | ||
---|---|---|---|
001 | wils-411201 | ||
005 | 202111110133 | ||
008 | 210211s2003 II a 000 eng D | ||
020 | # | # | |a 8184312458 |q paperback |
020 | # | # | |a 9788184312454 |q paperback |
040 | # | # | |a UiTM |b eng |c UiTM |e rda |
041 | 0 | # | |a eng |
090 | 0 | 0 | |a TK7868.D5 |b G63 2000 |
100 | 1 | # | |a Godse, Atul P. |e author |
245 | 1 | 0 | |a Digital Design & Computer Organisation |c Atul P. Godse, Deepali A. Godse |
246 | 0 | # | |a Digital Design and Computer Organisation |
250 | # | # | |a Third Revised Edition-2008 |
264 | # | 1 | |a Pune |b Technical Pub. Pune |c 2003 |
300 | # | # | |a xvi, 1 v. (various pagings) |b illustrations |c 25 cm |
336 | # | # | |a text |2 rdacontent |
337 | # | # | |a unmediated |2 rdamedia |
338 | # | # | |a volume |2 rdacarrier |
520 | # | # | |a Sequential Circuit Design : Synchronous and asynchronous FSM design, Basic design steps, State encoding techniques, VHDL coding of state machines, Analysis of sequential circuits, Algorithmic State Machine (ASM) charts. HDL : Introduction to HDL, VHDL, Library, Entity, Architecture, Modeling styles, Signals and variables, Sequential and concurrent statements, Synthesis and simulation concepts, Implementation of logic function. ALU Design : Addition and subtraction of signed numbers, Design of fast adders, Multiplication of positive numbers, Signed operand multiplication - Booth's algorithm, Fast multiplication - Bit pair recoding of multipliers. Carry save addition of summands. Integer division, Floating point numbers and operation, IEEE standards for floating point numbers, Arithmetic operations on floating point numbers, Guard bits and truncation, Implementing floating point operation. CPU Design : Memory operation, Instruction and instruction sequencing, Addressing modes, Assembly language, Basic input/output operations, Stacks and queues, Subroutines, Execution of a complete instruction, Multiple bus organization. Input/Output Organization : Accessing I/O devices, Interrupts, Direct memory access, Buses, Interface circuits. Memory Organization : Semiconductor RAM memory, Read only memory, Speed, Size and cost, Cache memories, Performance considerations, Virtual memories, Memory management requirements, Secondary storage. |
650 | # | 0 | |a Computer organization |
650 | # | 0 | |a Digital electronics |
700 | 1 | # | |a Godse, Deepali A. |e author |
856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=411201 |
964 | # | # | |c BOK |d 01 |
998 | # | # | |a 00130##a006.2.2||00250##a002.5.2||00250##b002.5.3||00255##a007.25.3||00260##a002.8.2||00260##b002.8.4||00260##c002.7.6||00264#1a002.8.2||00264#1b002.8.4||00300##a003.4.1||00300##b003.6.1||00300##c003.5.1||00500##a002.17.2||00502##a007.9.2||00520##a007.2||00520##b007.2||00538##a003.16.9||00546##a006.11||00730##a006.2.2||00730##d006.4||00730##f006.10||00730##n006.2.2||00730##p006.2.2|| |