Introduction to logic synthesis using Verilog HDL
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Unknown |
| Published: |
[San Rafael, Calif.]
Morgan & Claypool
2006
|
| Subjects: | |
| Online Access: | Click Here to View Status and Holdings. |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Add Tag MARC
| LEADER | 00000n a2200000 a 4501 | ||
|---|---|---|---|
| 001 | wils-406780 | ||
| 020 | # | # | |a 9781598294040 |
| 020 | # | # | |a 1598291068 |
| 040 | # | # | |a GAT |d ITMB |
| 090 | 0 | 0 | |a TK7868.L6 |b R44 2006 |
| 100 | 1 | # | |a Reese, Robert B. |d 1958- |q Robert Bryan |
| 245 | 1 | 0 | |a Introduction to logic synthesis using Verilog HDL |c Robert B. Reese, Mitchell A. Thornton |
| 260 | # | # | |a [San Rafael, Calif.] |b Morgan & Claypool |c 2006 |
| 300 | # | # | |a vii, 75 p. |b ill. |c 24cm |
| 504 | # | # | |a Includes bibliographical references |
| 650 | # | 0 | |a Electronic digital computers |x Design and construction |
| 650 | # | 0 | |a Computer hardware description languages |
| 650 | # | 0 | |a Verilog (Computer hardware description language) |x Design and construction |
| 650 | # | 0 | |a Logic design |x Computer programs |
| 700 | 1 | # | |a Thornton, Mitchell Aaron |
| 856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=406780 |
| 964 | # | # | |c BOK |d P1 |
| 998 | # | # | |a 00260##a002.8.2||00260##b002.8.4||00260##c002.7.6||00300##a003.4.1||00300##b003.6.1||00300##c003.5.1|| |
Verilog HDL digital design and modeling 
Verilog HDL Design Examples