Fully-depleted SOI CMOS circuits and technology for ultra-low power applications

Fully-depleted SOI CMOS circuits and technology for ultra-low power applications

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Bibliographic Details
Main Author: Sakurai, Takayasu
Other Authors: Matsuzawa, Akira, Douseki, Takakuni
Format: Unknown
Published: Dordrecht, The Netherlands Springer 2006
Subjects:
Metal oxide semiconductors, Complementary > Very large scale integration
Silicon-on-insulator technology
Low voltage systems
Integrated circuits > Very large scale integration
Online Access:Click Here to View Status and Holdings.
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245 1 0 |a Fully-depleted SOI CMOS circuits and technology for ultra-low power applications  |c by Takayasu Sakurai, Akira Matsuzawa and Takakuni Douseki 
260 # # |a Dordrecht, The Netherlands  |b Springer  |c 2006 
300 # # |a xv, 411 p.  |b ill.  |c 25 cm 
500 # # |a "The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society"--P. [4] of cover 
504 # # |a Includes bibliographical references and index 
650 # 0 |a Metal oxide semiconductors, Complementary  |x Very large scale integration 
650 # 0 |a Silicon-on-insulator technology 
650 # 0 |a Low voltage systems 
650 # 0 |a Integrated circuits  |x Very large scale integration 
700 1 # |a Matsuzawa, Akira 
700 # # |a Douseki, Takakuni 
856 4 0 |z Click Here to View Status and Holdings.  |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=383270 
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