Fully-depleted SOI CMOS circuits and technology for ultra-low power applications

Fully-depleted SOI CMOS circuits and technology for ultra-low power applications

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Bibliographic Details
Main Author: Sakurai, Takayasu
Other Authors: Matsuzawa, Akira, Douseki, Takakuni
Format: Unknown
Published: Dordrecht, The Netherlands Springer 2006
Subjects:
Metal oxide semiconductors, Complementary > Very large scale integration
Silicon-on-insulator technology
Low voltage systems
Integrated circuits > Very large scale integration
Online Access:Click Here to View Status and Holdings.
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Description
Item Description:"The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society"--P. [4] of cover
Physical Description:xv, 411 p. ill. 25 cm
Bibliography:Includes bibliographical references and index
ISBN:9780387292175 (hbk.)
0387292179 (hbk.)

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