System-on-chip test architectures nanometer design for testability

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Bibliographic Details
Other Authors:	Wang, Laung-Terng, Stroud, Charles E., Touba, Nur A.
Format:	Book
Published:	Amsterdam Boston Morgan Kaufmann Publishers 2008
Series:	The Morgan Kaufmann series in systems on silicon
Subjects:	Systems on a chip > Testing Integrated circuits > Very large scale integration > Testing Integrated circuits > Very large scale integration > Design
Online Access:	Click Here to View Status and Holdings.
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020	#	#	\|a 9780123739735 (hardcover : alk. paper)
020	#	#	\|a 012373973X (hardcover : alk. paper)
040	#	#	\|a DLC \|d ITMB
090	0	0	\|a TK7895.E42 \|b S978 2008
245	0	0	\|a System-on-chip test architectures \|b nanometer design for testability \|c edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
260	#	#	\|a Amsterdam \|a Boston \|b Morgan Kaufmann Publishers \|c 2008
300	#	#	\|a xxxvi, 856 p. \|b ill. \|c 25 cm
490	1	#	\|a The Morgan Kaufmann series in systems on silicon
504	#	#	\|a Includes bibliographical references and index
650	#	0	\|a Systems on a chip \|x Testing
650	#	0	\|a Integrated circuits \|x Very large scale integration \|x Testing
650	#	0	\|a Integrated circuits \|x Very large scale integration \|x Design
700	1	#	\|a Wang, Laung-Terng
700	#	#	\|a Stroud, Charles E.
700	#	#	\|a Touba, Nur A.
856	4	0	\|z Click Here to View Status and Holdings. \|u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=378521
964	#	#	\|c BOK \|d 01
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