SystemVerilog for verification a guide to learning the testbench language features

SystemVerilog for verification a guide to learning the testbench language features

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Bibliographic Details
Main Author:	Spear, Chris
Format:	Unknown
Published:	New York, NY Springer 2006
Subjects:	Verilog (Computer hardware description language) Integrated circuits > Verification
Online Access:	Click Here to View Status and Holdings.
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