Logic synthesis and verification algorithms
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| Format: | Unknown |
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New York
Springer
2006
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| Subjects: | |
| Online Access: | Click Here to View Status and Holdings. |
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| 001 | wils-347574 | ||
| 020 | # | # | |a 0387310053 |
| 020 | # | # | |a 0306475928 |
| 020 | # | # | |a 0387310045 (softcover : alk. paper) |
| 040 | # | # | |a DLC |d ITMB |
| 090 | 0 | 0 | |a TK7874.75 |b .H33 2002 |
| 100 | 1 | # | |a Hachtel, Gary D |
| 245 | 1 | 1 | |a Logic synthesis and verification algorithms |c Gary D. Hachtel, Fabio Somenzi |
| 260 | # | # | |a New York |b Springer |c 2006 |
| 300 | # | # | |a xxxii, 597 p. |b ill |c 24 cm |
| 504 | # | # | |a Includes bibliographical references and index |
| 650 | # | 0 | |a Computer-aided design |
| 650 | # | 0 | |a Logic design |x Data processing |
| 650 | # | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction |x Data processing |
| 650 | # | 0 | |a Integrated circuits |x Verification |
| 700 | 1 | # | |a Somenzi, Fabio |
| 856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=347574 |
| 964 | # | # | |c BOK |d 01 |
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Logic synthesis and verification algorithms