Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

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Bibliographic Details
Main Author: Hachtel, Gary D
Other Authors: Somenzi, Fabio
Format: Unknown
Published: New York Springer 2006
Subjects:
Computer-aided design
Logic design > Data processing
Integrated circuits > Very large scale integration > Design and construction > Data processing
Integrated circuits > Verification
Online Access:Click Here to View Status and Holdings.
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Description
Physical Description:xxxii, 597 p. ill 24 cm
Bibliography:Includes bibliographical references and index
ISBN:0387310053
0306475928
0387310045 (softcover : alk. paper)

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