Chip design for submicron vlsi cmos layout and simulation

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Bibliographic Details
Main Author:	Uyemura, John P.
Format:	Unknown
Published:	Toronto Thomson 2006
Subjects:	Integrated circuits > Very large scale integration > Design and construction Metal oxide semiconductors, Complementary > Design and construction
Online Access:	Click Here to View Status and Holdings.
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LEADER	00000n a2200000 a 4501
001	wils-331449
020	#	#	\|a 053446629X
020	#	#	\|a 9780534466299
040	#	#	\|a MIA \|d ITMB
090	0	0	\|a TK7871.99.M44 \|b U9195 2006
100	1	#	\|a Uyemura, John P.
245	1	1	\|a Chip design for submicron vlsi \|b cmos layout and simulation \|c John P.Uyemura
246	1	#	\|a CMOS layout and simulation
260	#	#	\|a Toronto \|b Thomson \|c 2006
300	#	#	\|a xvi, 411 p. \|b ill. \|c 25 cm. + \|e 1 CD-ROM (4 3/4 in.)
504	#	#	\|a Includes bibliographical references and index
538	#	#	\|a Minimum system requirements: Windows 98SE, XP, 2000 or NT 64 MB system RAM; Pentium or compatible CPU
650	#	0	\|a Integrated circuits \|x Very large scale integration \|x Design and construction
650	#	0	\|a Metal oxide semiconductors, Complementary \|x Design and construction
856	4	0	\|z Click Here to View Status and Holdings. \|u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=331449
964	#	#	\|c BOK \|d 01
998	#	#	\|a 00260##a002.8.2\|\|00260##b002.8.4\|\|00260##c002.7.6\|\|00300##a003.4.1\|\|00300##b003.6.1\|\|00300##c003.5.1\|\|00538##a003.16.9\|\|