Design through Verilog HDL
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Format: | Unknown |
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Hoboken, NJ
John Wiley IEEE Press
2004
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Online Access: | Click Here to View Status and Holdings. |
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LEADER | 00000n a2200000 a 4501 | ||
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001 | wils-312592 | ||
020 | # | # | |a 0471441481 (cloth) |
090 | 0 | 0 | |a TK7885.7 |b .P37 2004 |
100 | 1 | # | |a Patma?n?apa?n, ?Ti. ?Ar |
245 | 1 | 1 | |a Design through Verilog HDL |c T.R. Padmanabhan, B. Bala Tripura Sundari |
260 | # | # | |a Hoboken, NJ |b John Wiley |b IEEE Press |c 2004 |
300 | # | # | |a xii, 455 p. |b ill. |c 25 cm |
504 | # | # | |a Includes bibliographical references (p. 449-450) and index |
650 | # | 0 | |a Verilog (Computer hardware description language) |
700 | 1 | # | |a Tripura Sundari, B. Bala |
856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=312592 |
964 | # | # | |c BOK |d 01 |
040 | # | # | |a Shah Alam |
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