Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

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Bibliographic Details
Main Author:	Hachtel, Gary D.
Other Authors:	Somenzi, Fabio
Format:	Unknown
Published:	Boston Kluwer Academic Publishersr 1996
Subjects:	Login design > Data processing Integrated circuits > Verification Integrated circuits > Very large scale integration > Design > Data processing
Online Access:	Click Here to View Status and Holdings.
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