Logic synthesis and verification algorithms

Logic synthesis and verification algorithms

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Bibliographic Details
Main Author: Hachtel, Gary D.
Other Authors: Somenzi, Fabio
Format: Unknown
Published: Boston Kluwer Academic Publishersr 1996
Subjects:
Login design > Data processing
Integrated circuits > Verification
Integrated circuits > Very large scale integration > Design > Data processing
Online Access:Click Here to View Status and Holdings.
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090 0 0 |a TK7874.75  |b .H33 1996 
100 1 # |a Hachtel, Gary D. 
245 1 1 |a Logic synthesis and verification algorithms  |c by Gary D. Hachtel, Fabio Somenzi 
260 # # |a Boston  |b Kluwer Academic Publishersr  |c 1996 
300 # # |a xxiii, 564 p.  |b ill.  |c 24 cm 
504 # # |a Includes bibliographical references and index 
650 # 0 |a Login design  |x Data processing 
650 # 0 |a Integrated circuits  |x Verification 
650 # 0 |a Integrated circuits  |x Very large scale integration  |x Design  |x Data processing 
700 1 # |a Somenzi, Fabio 
856 4 0 |z Click Here to View Status and Holdings.  |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=210178 
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040 # # |a Shah Alam 
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