Genetic algorithms for VLSI design, layout & test automation
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Format: | Unknown |
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Upper Saddle River, N.J.
Prentice Hall PTR
1999
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Online Access: | Click Here to View Status and Holdings. |
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LEADER | 00000n a2200000 a 4501 | ||
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001 | wils-206888 | ||
020 | # | # | |a 0130115665 |
090 | 0 | 0 | |a TK7874.75 |b .M39 1999 |
100 | 1 | # | |a Mazumder, Pinaki |
245 | 1 | 1 | |a Genetic algorithms for VLSI design, layout & test automation |c Pinaki Mazumder, Elizabeth M. Rudnick |
260 | # | # | |a Upper Saddle River, N.J. |b Prentice Hall PTR |c 1999 |
300 | # | # | |a xiii, 338 p. |b ill. |c 25 cm. |
504 | # | # | |a Includes bibliographical references and index |
650 | # | 0 | |a Genetic algorithms |
650 | # | 0 | |a Integrated circuits |x Very large scale integration |x Testing |
700 | 1 | # | |a Rudnick, Elizabeth M |
856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=206888 |
964 | # | # | |c BOK |d 01 |
040 | # | # | |a Shah Alam |
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