VHDL for simulation, synthesis and formal proofs of hardware
Saved in:
Other Authors: | |
---|---|
Format: | Book |
Published: |
Dordrecht
Kluwer Academic
1992
|
Series: | The Kluwer international series in engineering and computer science, SECS 183
|
Subjects: | |
Online Access: | Click Here to View Status and Holdings. |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
MARC
LEADER | 00000n a2200000 a 4501 | ||
---|---|---|---|
001 | wils-184144 | ||
020 | # | # | |a 0792392531 |
090 | 0 | 0 | |a TK7885.7 |b .V48 1992 |
245 | 1 | 1 | |a VHDL for simulation, synthesis and formal proofs of hardware |c edited by Jean Mermet |
260 | # | # | |a Dordrecht |b Kluwer Academic |c 1992 |
300 | # | # | |a ix, 307 p. |b ill. |c 25 cm |
490 | 1 | # | |a The Kluwer international series in engineering and computer science, SECS 183 |
504 | # | # | |a Includes bibliographical references |
650 | # | 0 | |a VHDL (Computer hardware description language) |
700 | 1 | # | |a Mermet, Jean P |
856 | 4 | 0 | |z Click Here to View Status and Holdings. |u https://opac.uitm.edu.my/opac/detailsPage/detailsHome.jsp?tid=184144 |
964 | # | # | |c BOK |d 01 |
040 | # | # | |a Shah Alam |